Motivated by the ongoing growth in demand for microchips, high production costs and the complex interplay of human, machine, material and method (4M), suppliers strive to develop more advanced production planning and control regimes for semiconductor production. Batching decisions often dramatically influence the overall performance of wafer fabs in terms of capacity utilization, due date compliance, cycle time and variability. To optimize such processes, we present an integrated testbed for batch formation optimization. Using a simulation of multiple semiconductor work centers, we explore how to optimize work in progress (WIP) flow with a continuous real-time scheduler and previously published batch formation heuristics. The proposed solver is designed to only optimize capacity-limited operations. By considering real-world operations requirements and semiconductor process specifics such as qualification criteria and re-entrance in our model, we demonstrate how to realize significant throughput gains. We explore and demonstrate the developed digital twin through a powerful BI frontend for historical analysis and real-time shop floor monitoring.
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