FPGA-accelerated phase rectification for a stereo-based phase measuring profilometry system

This paper proposes a FPGA-accelerated lens undistortion and rectification algorithm for a stereo-based phase measuring profilometry system. After a brief system overview we go into detail on the proposed hardware architecture for the stereo rectification block. The hardware architecture is based on a Xilinx Zynq-7020 SoC and uses compressed rectification maps to reduce the memory load. As a result, it is able to rectify a stereo setup with 435 mm baseline and converged optical axis of 32° between the cameras. The cameras are configured with 2 Mpix @ 60 fps and rectification can be applied "on the fly" during image grabbing.