SoC-based real-time passive stereo image processing implementation and optimization
Stereo Image Processing as a part of three dimensional image processing become more and more important for industrial measuring, quality assurance and industrial automation. While classical image processing get it features from an image plane, additional information is obtained in direction of the optical axis. In comparison to active stereo methods, which need a projector or laser source and scanning device, passive stereo need at minimum two images from different perspectives. The paper starts with the basics of passive stereo, required optical setup and electronics. Some Information about the implementation of a stereo IP core in the used Xilinx SoC FPGA embedded system given. The program flow in ARM core and FPGA is illustrated. To get a high performance image processing system, the optimization of the parameters and the implementation settings on the used FPGA is very important. A comparison of several core parameter setups is done. Finally, some ways for further optimization with new hardware technologies are given.